Integrated circuits are connectable to external circuitry through input nodes, output nodes, or input/output nodes such as bond pads, input pads, input/output pins, die terminals, die pads, contact pads, and so forth. The integrated circuitry often includes operational circuitry that includes circuit components, such as transistors, that are susceptible to damage caused by over-limit electrical events, for example, voltages caused by electrostatic discharge (ESD) during handling, testing and operation of the integrated circuit. An over-limit electrical event (e.g., an ESD event) that may cause damage to the circuitry of the integrated circuit unless adequately protected. Typically, the susceptible circuit components may be protected from over-limit electrical events via an ESD protection circuit to prevent damage caused by an over-limit electrical event. Typically, an ESD protection circuit is associated with one of the above-mentioned nodes.
ESD protection circuits may include circuitry that provides a conductive path to a reference voltage such as ground and/or to a voltage supply such as VCC, to limit or clamp the voltage (e.g., by discharging or shunting the current) associated with the over-limit electrical event before operational circuitry of the integrated circuit is damaged. Although some circuit components may be capable of limiting some transient ESD voltage without some circuit components may be capable of limiting some transient ESD voltage without damaging circuit components, other circuit components may be damaged as a result of any ESD voltage. For example, high-speed input or output circuits (or other specialized circuit components) may tolerate little to no transient ESD voltage or current. In other words, some circuits may not be self-protecting. Also, as semiconductor devices continue to shrink, the circuit components become more prone to and less tolerant of over-limit electrical events. And, even if the circuit components can tolerate a small level of transient ESD voltage or current, the ESD protection circuit's breakdown voltage may be lower than the breakdown voltage of for example, the circuit components. In this case, dedicated ESD circuits may be added to help clamp the ESD voltage level below the breakdown voltage of the transistors.
Some dedicated ESD circuits include circuit components that exhibit a “snap-back” characteristic. Generally, a snap-back characteristic provides a trigger condition which, when exceeded, causes the circuit to enter a low-impedance state. The low-impedance state is maintained while the electrical condition on the node exceeds a minimum hold condition (e.g., minimum holding voltage and/or current levels). Examples of conventional circuits having snapback characteristics include overdriven metal-oxide-semiconductor (MOS) transistors.
In designing an adequate protection circuit using a snapback circuit, the trigger condition must be sufficiently low to provide protection before a breakdown condition occurs for operational circuitry. Examples of conventional protection circuit for operational circuitry coupled to a negative potential node may include an ESD clamp formed using large p-type field-effect transistors (PFETs). In this case, for example, should a large negative voltage (with respect to a reference voltage, such as ground) from an over-limit electrical event be provided to the node, the transient ESD voltages may be limited and the ESD current may be discharged through the large ESD clamp to ground. However, the large ESD clamp requires a large footprint to implement. An ESD voltage protection circuit is capable of protecting the operation circuitry, yet requiring a smaller footprint is desirable.